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general description the max5891 advanced 16-bit, 600msps, digital-to- analog converter (dac) meets the demanding perfor- mance requirements of signal synthesis applications found in wireless base stations and other communica- tions applications. operating from +3.3v and +1.8v supplies, the max5891 dac supports update rates of 600msps using high-speed lvds inputs while consum- ing only 298mw of power and offers exceptional dynamic performance such as 80dbc spurious-free dynamic range (sfdr) at f out = 30mhz. the max5891 utilizes a current-steering architecture that supports a 2ma to 20ma full-scale output current range, and produces -2dbm to -22dbm full-scale output signal levels with a double-terminated 50 ? load. the max5891 features an integrated +1.2v bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. a separate reference input (refio) allows for the use of an external reference source for optimum flexibility and improved gain accuracy. the max5891 digital inputs accept lvds voltage lev- els, and the flexible clock input can be driven differen- tially or single-ended, ac- or dc-coupled. the max5891 is available in a 68-pin qfn package with an exposed paddle (ep) and is specified for the extended (-40? to +85?) temperature range. refer to the max5890* and MAX5889* data sheets for pin-compatible 14-bit and 12-bit versions of the max5891. applications base stations: single/multicarrier umts, cdma, gsm communications: fixed broadband wireless access, point-to-point microwave direct digital synthesis (dds) cable modem termination systems (cmts) automated test equipment (ate) instrumentation features ? 600msps output update rate ? low noise spectral density: -163dbfs/hz at f out = 36mhz ? excellent sfdr and imd performance sfdr = 80dbc at f out = 30mhz (to nyquist) sfdr = 69dbc at f out = 130mhz (to nyquist) imd = -94dbc at f out = 30mhz imd = -77dbc at f out = 130mhz ? aclr = 73db at f out = 122.88mhz ? 2ma to 20ma full-scale output current ? lvds-compatible digital inputs ? on-chip +1.2v bandgap reference ? low 298mw power dissipation at 600msps ? compact (10mm x 10mm) qfn-ep package ? evaluation kit available (max5891evkit) max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs ________________________________________________________________ maxim integrated products 1 ordering information 19-3542; rev 0; 2/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package pkg code max5891egk -40 c to +85 c 68 qfn-ep** g6800-4 max5891 +1.2v reference refio dacref fsadj clk interface 600mhz 16-bit dac latch l vds receiver d0?15 l vds data inputs power down pd clkp clkn outp outn functional diagram part resolution (bits) update rate ( msps) logic input MAX5889* 12 600 lvds max5890* 14 600 lvds max5891 16 600 lvds selector guide * future product?ontact factory for availability. ** ep = exposed paddle. pin configuration appears at end of data sheet.
max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, external reference v refio = +1.2v, output load 50 ? double-ter- minated, transformer-coupled output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. specifications at t a +25? are guaranteed by production testing. specifications at t a < +25? are guaranteed by design and characterization. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd1.8 , dv dd1.8 to agnd, dgnd, dacref, and cgnd.......................................................-0.3v to +2.16v av dd3.3 , dv dd3.3 , av clk to agnd, dgnd, dacref, and cgnd.........................................-0.3v to +3.9v refio, fsadj to agnd, dacref, dgnd, and cgnd ..........................-0.3v to (av dd3.3 + 0.3v) outp, outn to agnd, dgnd, dacref, and cgnd .......................................-1.2v to (av dd3.3 + 0.3v) clkp, clkn to agnd, dgnd, dacref, and cgnd..........................................-0.3v to (av clk + 0.3v) pd to agnd, dgnd, dacref, and cgnd.......................................-0.3v to (dv dd3.3 + 0.3v) digital data inputs (d0n?15n, d0p?15p) to agnd, dgnd, dacref, and cgnd ..........-0.3v to (dv dd1.8 + 0.3v) continuous power dissipation (t a = +70?) (note 1) 68-pin qfn-ep (derate 28.6mw/? above +70?)....3333mw thermal resistance ja (note 1) ....................................24?/w operating temperature range ..........................-40? to +85? junction temperature .....................................................+150? storage temperature range ............................-60? to +150? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units static performance resolution 16 bits integral nonlinearity inl measured differentially ?.8 lsb differential nonlinearity dnl measured differentially ?.6 lsb offset error os -0.02 0.001 +0.02 %fs full-scale gain error ge fs external reference -4 ? +4 %fs internal reference 130 gain-drift tempco external reference 100 ppm/ c full-scale output current i out 220ma output compliance single-ended -1.0 +1.1 v output resistance r out 1m ? output capacitance c out 5pf output leakage current pd = high, power-down mode 1a dynamic performance maximum dac update rate 600 msps minimum dac update rate 1 msps f out = 36mhz a full-scale = -3.5dbm -163 noise spectral density n f clk = 500mhz, -12dbfs, 20mhz offset from the carrier f out = 151mhz a full-scale = -6.4dbm -155 dbfs/hz f out = 36mhz 70 signal-to-noise ratio over nyquist snr f clk = 500mhz, 0dbfs f out = 151mhz 64 db note 1: thermal resistance based on a multilayer board with 4x4 via array in exposed paddle area
max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, external reference v refio = +1.2v, output load 50 ? double-ter- minated, transformer-coupled output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. specifications at t a +25? are guaranteed by production testing. specifications at t a < +25? are guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units f out = 16mhz 86 f clk = 200mhz, 0dbfs f out = 30mhz 84 f out = 16mhz 76 f clk = 200mhz, -12dbfs f out = 30mhz 76 f out = 16mhz 77 84 f out = 30mhz 80 f out = 130mhz 69 spurious-free dynamic range to nyquist sfdr f clk = 500mhz, 0dbfs f out = 200mhz 63 dbc f clk = 500mhz f out1 = 29mhz, f out2 = 30mhz, -6.5dbfs per tone -94 two-tone imd ttimd f clk = 500mhz f out1 = 129mhz, f out2 = 130mhz, -6.5dbfs per tone -77 dbc f clk = 491.52mhz, f out = 30.72mhz 82 wcdma single carrier f clk = 491.52mhz, f out = 122.88mhz 73 f clk = 491.52mhz, f out = 30.72mhz 74 adjacent channel leakage power ratio aclr wcdma four carriers f clk = 491.52mhz, f out = 122.88mhz 67 db output bandwidth bw -1db (note 2) 1000 mhz reference internal reference voltage range v refio 1.14 1.2 1.26 v reference input voltage range v refiocr using external reference 0.10 1.2 1.32 v reference input resistance r refio 10 k ? reference voltage temperature drift tco ref 50 ppm/ c
max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, external reference v refio = +1.2v, output load 50 ? double-ter- minated, transformer-coupled output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. specifications at t a +25? are guaranteed by production testing. specifications at t a < +25? are guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units analog output timing (figure 3) output fall time t fall 90% to 10% (note 3) 0.4 ns output rise time t rise 10% to 90% (note 3) 0.4 ns output propagation delay t pd reference to data latency (note 3) 2.5 ns output settling time to 0.025% of the final value (note 3) 11 ns glitch impulse measured differentially 1 pv ? s i out = 2ma 30 output noise n out i out = 20ma 30 pa/ hz h input data rate 600 mwps data latency 5.5 clock cycles data to clock setup time t setup referenced to rising edge of clock (note 4) -1.2 ns data to clock hold time t hold referenced to rising edge of clock (note 4) 2ns clock frequency f clk clkp, clkn 600 mhz minimum clock pulse-width high t ch clkp, clkn 0.6 ns minimum clock pulse-width low t cl clkp, clkn 0.6 ns turn-on time t shdn external reference, pd falling edge to output settle within 1% 350 ? cmos logic input (pd) input logic high v ih 0.7 x dv dd3.3 v input logic low v il 0.3 x dv dd3.3 v input current i in -5 1.8 +5 ? input capacitance c in 3pf lvds inputs differential input high v ihlvds +100 mv differential input low v illvds -100 mv common-mode voltage range v icmlvds 1.125 1.375 v differential input resistance r idlvds 110 ? ? input capacitance c inlvds 3pf differential clock inputs (clkp, clkn) clock common-mode voltage clkp and clkn are internally biased av clk / 2 v minimum differential input voltage swing 0.5 v p-p
max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs _______________________________________________________________________________________ 5 note 2: this parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the max5891. note 3: parameter measured single-ended with 50 ? double-terminated outputs. note 4: not production tested. guaranteed by design. note 5: parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltages. electrical characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, external reference v refio = +1.2v, output load 50 ? double-ter- minated, transformer-coupled output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. specifications at t a +25? are guaranteed by production testing. specifications at t a < +25? are guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units minimum common-mode voltage 1v maximum common-mode voltage 1.9 v input resistance r clk single-ended 5 k ? input capacitance c clk 3pf power supplies av dd3.3 3.135 3.3 3.465 analog supply voltage range av dd1.8 1.710 1.8 1.890 v clock supply voltage range av clk 3.135 3.3 3.465 v dv dd3.3 3.135 3.3 3.465 digital supply voltage range dv dd1.8 1.710 1.8 1.890 v f clk = 100mhz, f out = 16mhz 26.5 f clk = 500mhz, f out = 16mhz 26.5 28 i avdd3.3 f clk = 600mhz, f out = 16mhz 26.5 f clk = 100mhz, f out = 16mhz 11.3 f clk = 500mhz, f out = 16mhz 50 58 analog supply current i avdd1.8 f clk = 600mhz, f out = 16mhz 61 ma f clk = 100mhz, f out = 16mhz 2.8 f clk = 500mhz, f out = 16mhz 2.8 3.6 clock supply current i avclk f clk = 600mhz, f out = 16mhz 2.8 ma f clk = 100mhz, f out = 16mhz 0.2 f clk = 500mhz, f out = 16mhz 0.2 0.5 i dvdd3.3 f clk = 600mhz, f out = 16mhz 0.2 f clk = 100mhz, f out = 16mhz 10.6 f clk = 500mhz, f out = 16mhz 44 50 digital supply current i dvdd1.8 f clk = 600mhz, f out = 16mhz 50.5 ma f clk = 100mhz, f out = 16mhz 137 f clk = 500mhz, f out = 16mhz 267 301 f clk = 600mhz, f out = 16mhz 298 mw total power dissipation p diss power-down, clock static low, data input static 13 w power-supply rejection ratio psrr (note 5) 0.025 %fs
max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs 6 _______________________________________________________________________________________ t ypical operating characteristics (av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, external reference v refio = +1.2v, output load 50 ? double-ter- minated, transformer-coupled output, i out = 20ma, t a = +25?, unless otherwise noted.) spurious-free dynamic range vs. output frequency (f clk = 100mhz) max5891 toc01 output frequency (mhz) sfdr (dbc) 30 20 10 10 20 30 40 50 60 70 80 90 100 0 040 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 200mhz) max5891 toc02 output frequency (mhz) sfdr (dbc) 70 60 40 50 20 30 10 10 20 30 40 50 60 70 80 90 100 0 080 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 500mhz) max5891 toc03 output frequency (mhz) sfdr (dbc) 160 120 80 40 10 20 30 40 50 60 70 80 90 100 0 0 200 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 600mhz) max5891 toc04 output frequency (mhz) sfdr (dbc) 160 120 80 40 10 20 30 40 50 60 70 80 90 100 0 0 200 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 500mhz, i out = 20ma, 10ma, 5ma) max5891 toc05 output frequency (mhz) sfdr (dbc) 160 120 80 40 10 20 30 40 50 60 70 80 90 100 0 0 200 20ma 10ma 5ma dac output spectral plot (f clk = 200mhz) max5891 toc06 output frequency (mhz) output power (dbm) 80 60 40 20 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 100 70 50 30 10 90 dac output spectral plot (f clk = 500mhz) max5891 toc07 output frequency (mhz) 200 150 100 50 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 0 250 output power (dbm) two-tone spectral plot (f clk = 500mhz, -6.5dbfs per tone) max5891 toc08 output frequency (mhz) 131 130 129 128 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 127 132 output power (dbm) two-tone spectral plot (f clk = 500mhz, -6.5dbfs per tone) max5891 toc09 output frequency (mhz) 31 30 29 28 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 27 32 output power (dbm)
max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs _______________________________________________________________________________________ 7 two-tone intermodulation distortion vs. output frequency (f clk = 500mhz, 1mhz carrrier spacing) max5891 toc10 output frequency (mhz) sfdr (dbc) 160 120 80 40 -110 -100 -90 -80 -70 -60 -120 0 200 -6.5dbfs -12dbfs single-carrier wcdma aclr (f clk = 491.52mhz) output power (dbm) max5891 toc11 aclr = 72.3db f center = 122.88mhz 2.5mhz/div -20 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 four-carrier wcdma aclr (f clk = 491.52mhz) max5891 toc12 4.06mhz/div output power (dbm) aclr = 67.3db f center = 122.88mhz -20 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 spurious-free dynamic range vs. temperature (f clk = 500mhz) max5891 toc13 temperature ( c) sfdr (dbc) 60 35 10 -15 60 70 80 90 100 50 -40 85 f out = 10mhz f out = 50mhz f out = 100mhz integral nonlinearity max5891 toc14 digital input code inl (lsb) 57344 49152 8192 16384 24576 32768 40960 -3 -2 -1 0 1 2 3 4 -4 0 65536 differential nonlinearity max5891 toc15 digital input code dnl (lsb) 57344 49152 8192 16384 24576 32768 40960 -3 -2 -1 0 1 2 -4 0 65536 total power dissipation vs. clock frequency (f out = 16mhz, a out = 0dbfs) max5891 toc16 clock frequency (mhz) power dissipation (mw) 500 400 300 200 100 50 100 150 200 250 300 350 0 0 600 t ypical operating characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, external reference v refio = +1.2v, output load 50 ? double-ter- minated, transformer-coupled output, i out = 20ma, t a = +25?, unless otherwise noted.)
max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs 8 _______________________________________________________________________________________ pin name function 1, 3, 5, 7, 9, 46, 48, 50, 52, 54, 56, 58, 60, 63, 65, 67 d4n, d3n, d2n, d1n, d0n, d15n, d14n, d13n, d12n, d11n, d10n, d9n, d8n, d7n, d6n, d5n differential negative lvds inputs. data bits d0?15 (offset binary format). 2, 4, 6, 8, 45, 47, 49, 51, 53, 55, 57, 59, 62, 64, 66, 68 d3p, d2p, d1p, d0p, d15p, d14p, d13p, d12p, d11p, d10p, d9p, d8p, d7p, d6p, d5p, d4p differential positive lvds inputs. data bits d0?15 (offset binary format). 10 dgnd digital ground. ground return for dv dd3.3 and dv dd1.8 . 15, 20, 23, 24, 27, 30, 33 agnd analog ground. ground return for av dd3.3 and av dd1.8 . 11 dv dd3.3 digital supply voltage. accepts a 3.135v to 3.465v supply voltage range. bypass with a 0.1? capacitor to dgnd. 12 pd power-down input. set pd high to force the dac into power-down mode. set pd low for normal operation. pd has an internal 2? pulldown. 13, 42, 43, 44 n.c. no connection. leave floating or connect to agnd. 14, 21, 22, 25, 26, 31, 32 av dd3.3 analog supply voltage. accepts a 3.135v to 3.465v supply voltage range. bypass with a 0.1? capacitor to agnd. 16 refio reference i/o. output of the internal 1.2v precision bandgap reference. bypass with a 0.1? capacitor to agnd. refio can be driven with an external reference source. 17 fsadj full-scale current adjustment. connect an external resistor r set between fsadj and dacref to set the output full-scale current. the output full-scale current is equal to 32 x v ref / r set . 18 dacref current-set resistor return path. internally connected to ground, but do not use as ground connection. 19, 34, 35 av dd1.8 analog supply voltage. accepts a 1.71v to 1.89v supply voltage range. bypass with a 0.1? capacitor to agnd. 28 outn complementary dac output. negative terminal for current output. 29 outp dac output. positive terminal for current output. 36, 41 av clk clock supply voltage. accepts a 3.135v to 3.465v supply voltage range. bypass with a 0.1? capacitor to cgnd. 37, 40 cgnd clock supply ground 38 clkn complementary converter clock input. negative input terminal for differential converter clock. 39 clkp converter clock input. positive input terminal for differential converter clock. 61 dv dd1.8 digital supply voltage. accepts a 1.71v to 1.89v supply voltage range. bypass with a 0.1? capacitor to dgnd. ?p exposed pad. must be connected to common point for agnd, dgnd, and cgnd through a low-impedance path. ep is internally connected to agnd, dgnd, and cgnd. pin description
detailed description architecture the max5891 high-performance, 16-bit, current-steer- ing dac (see the functional diagram ) operates with dac update rates up to 600msps. the current-steering array generates differential full-scale currents in the 2ma to 20ma range. an internal current-switching net- work, in combination with external 50 ? termination resistors, converts the differential output currents into a differential output voltage with a 0.1v to 1v peak-to- peak output voltage range. the analog outputs have a -1.0v to +1.1v voltage compliance. for applications requiring high dynamic performance, use the differen- tial output configuration and limit the output voltage swing to ?.5v at each output. an integrated +1.2v bandgap reference, control amplifier, and user-selec- table external resistor determine the data converter? full-scale output range. reference architecture and operation the max5891 operates with the internal +1.2v bandgap reference or an external reference voltage source. refio serves as the input for an external, low- impedance reference source or as a reference output when the dac operates in internal reference mode. for stable operation with the internal reference, bypass refio to agnd with a 0.1? capacitor. the refio out- put resistance is 10k ? . buffer refio with a high-input- impedance amplifier when using it as a reference source for external circuitry. the max5891? reference circuit (figure 1) employs a control amplifier to regulate the full-scale current, i outfs , for the differential current outputs of the dac. calculate the output current as follows: where i outfs is the full-scale output current of the dac. r set (located between fsadj and dacref) determines the amplifier? full-scale output current for the dac. see table 1 for a matrix of different i outfs and r set selections. analog outputs (outp, outn) the complementary current outputs (outp, outn) can be connected in a single-ended or differential configu- ration. a load resistor converts these two output cur- rents into complementary single-ended output voltages. a transformer or a differential amplifier con- verts the differential voltage existing between outp and outn to a single-ended voltage. when not using a transformer, terminate each output with a 25 ? resistor to ground and a 50 ? resistor between the outputs. to generate a single-ended output, select outp as the output and connect outn to agnd. figure 2 shows a simplified diagram of the internal output structure of the max5891. i v r outfs refio set = ? ? ? ? ? ? ? 32 1 1 2 16 max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs _______________________________________________________________________________________ 9 r set ( ? ) full-scale current i outfs (ma) calculated 1% eia std 2 19.2k 19.1k 5 7.68k 7.5k 10 3.84k 3.83k 15 2.56k 2.55k 20 1.92k 1.91k table 1. i outfs and r set selection matrix based on a typical +1.200v reference voltage outp outn +1.2v reference current-source array dac refio fsadj r set i ref 10k ? dacref 0.1 f i ref = v refio / r set figure 1. reference architecture, internal reference configuration
max5891 clock inputs (clkp, clkn) to achieve the best possible jitter performance, the max5891 features flexible differential clock inputs (clkp, clkn) that operate from a separate clock power supply (av clk ). drive the differential clock inputs from a single-ended or a differential clock source. for highest dynamic performance, differential clock source is required. for single-ended operation, drive clkp with a logic source and bypass clkn to cgnd with a 0.1? capacitor. clkp and clkn are internally biased at av clk / 2, allowing the ac-coupling of clock sources directly to the device without external resistors to define the dc level. the input resistance from clkp and clkn to ground is approximately 5k ? . data-timing relationship figure 3 shows the timing relationship between digital lvds data, clock, and output signals. the max5891 features a 2ns hold, a -1.2ns setup, and a 2.5ns propa- gation delay time. there is a 5.5 clock-cycle latency between data write operation and the corresponding analog output transition. lvds data inputs the max5891 has 16 pairs of lvds data inputs (offset binary format) and can accept data rates up to 600mwps. each differential input pair is terminated with an internal 110 ? resistor. the common-mode input resistance is 3.2k ? . power-down operation (pd) the max5891 features a power-down mode that reduces the dac? power consumption. set pd high to power down the max5891. set pd low or leave uncon- nected for normal operation. when powered down, the max5891 overall power con- sumption is reduced to less than 13?. the max5891 requires 350? to wake up from power-down and enter a fully operational state if the external reference is used. if the internal reference is used, the power-down recovery time is 10ms. the pd internal pulldown circuit sets the max5891 in normal mode when pd is left unconnected. 16-bit, 600msps, high-dynamic-performance dac with lvds inputs 10 ______________________________________________________________________________________ i out i out outn outp current sources current switches av dd3.3 figure 2. simplified analog output structure d0?16 t setup t hold d n clkp clkn d n + 2 d n + 4 d n + 6 ioutp ioutn t pd d n + 1 d n + 3 d n + 5 d n + 7 out n - 2 out n - 3 out n - 4 out n - 5 out n - 6 out n - 7 out n-1 out n figure 3. timing relationship between clock, input data, and analog output
applications information clock interface to achieve the best possible jitter performance, the max5891 features flexible differential clock inputs (clkp, clkn) that operate from a separate clock power supply (av clk ). use a low-jitter clock to reduce the dac? phase noise and wideband noise. to achieve the best dac dynamic performance, the clkp/clkn input source must be designed carefully. the differential clock (clkn and clkp) input can be driven from a single-ended or a differential clock source. use differential clock drive to achieve the best dynamic performance from the dac. for single-ended operation, drive clkp with a low noise source and bypass clkn to cgnd with a 0.1? capacitor. figure 4 shows a convenient and quick way of applying a differential signal created from a single-ended source using a wideband transformer. alternatively, drive clkp/clkn from a cmos-compatible clock source. use sinewave or ac-coupled differential ecl/pecl drive for best dynamic performance. differential output coupling using a wideband rf transformer use a pair of transformers (figure 5) or a differential amplifier configuration to convert the differential voltage existing between outp and outn to a single-ended voltage. optimize the dynamic performance by using a differential transformer-coupled output and limit the out- put power to <0dbm full scale. to achieve the best dynamic performance, use the differential transformer configuration. terminate the dac as shown in figure 5, and use 50 ? termination at the transformer single- ended output. this will provide double 50 ? termination for the dac output network. with the double-terminated output and 20ma full-scale current, the dac will pro- duce a full-scale signal level of approximately -2dbm. pay close attention to the transformer core saturation characteristics when selecting a transformer for the max5891. transformer core saturation can introduce strong 2nd-order harmonic distortion especially at low output frequencies and high signal amplitudes. for best results, connect the center tap of the transformer to ground. when not using a transformer, terminate each dac output to ground with a 25 ? resistor. additionally, place a 50 ? resistor between the outputs (figure 6). for a single-ended unipolar output, select outp as the output and connect outn to agnd. operating the max5891 single-ended is not recommended because it degrades the dynamic performance. the distortion performance of the dac depends on the load impedance. the max5891 is optimized for 50 ? differential double termination. using higher termination impedance degrades distortion performance and increases output noise voltage. max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs ______________________________________________________________________________________ 11 wideband rf transformer performs single-ended-to- differential conversion single-ended clock source agnd 1:1 25 ? 25 ? clkp clkn to dac 0.1 f 0.1 f figure 4. differential clock-signal generation max5891 outp outn wideband rf transformer t2 performs the differential-to-single-ended conversion t1, 1:1 t2, 1:1 agnd 50 ? 100 ? 50 ? v out , single-ended d0?15 l vds data inputs figure 5. differential-to-single-ended conversion using a wideband rf transformer
max5891 grounding, bypassing, and power-supply considerations grounding and power-supply decoupling strongly influ- ence the max5891 performance. unwanted digital crosstalk coupling through the input, reference, power supply, and ground connections affects dynamic per- formance. high-speed, high-frequency applications require closely followed proper grounding and power- supply decoupling. these techniques reduce emi and internal crosstalk that can significantly affect the max5891 dynamic performance. use a multilayer printed circuit (pc) board with sepa- rate ground and power-supply planes. run high-speed signals on lines directly above the ground plane. keep digital signals as far away from sensitive analog inputs and outputs, reference input sense lines, common- mode inputs, and clock inputs as practical. use a sym- metric design of clock input and the analog output lines to minimize 2nd-order harmonic distortion components, thus optimizing the dac? dynamic performance. keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches. the max5891 requires five separate power-supply inputs for analog (av dd1.8 and av dd3.3 ), digital (dv dd1.8 and dv dd3.3 ), and clock (av clk ) circuitry. decouple each av dd3.3 , av dd1.8 , av clk , dv dd3.3 , and dv dd1.8 input with a separate 0.1? capacitor as close to the device as possible with the shortest possible con- nection to the respective ground plane (figure 7). connect all of the 3.3v supplies together at one point with ferrite beads to minimize supply noise coupling. decouple all five power-supply voltages at the point they enter the pc board with tantalum or electrolytic capaci- tors. ferrite beads with additional decoupling capacitors forming a pi network can also improve performance. similarly, connect all 1.8v supplies together at one point with ferrite beads. the analog and digital power-supply inputs av dd3.3 , av clk , and dv dd3.3 allow a +3.135v to +3.465v sup- ply voltage range. the analog and digital power-supply inputs av dd1.8 and dv dd1.8 allow a +1.71v to +1.89v supply voltage range. the max5891 is packaged in a 68-pin qfn-ep pack- age with exposed paddle, providing optimized dac ac performance. the exposed pad must be soldered to the ground plane of the pc board. thermal efficiency is not the key factor, since the max5891 features low- power operation. the exposed pad ensures a solid ground connection between the dac and the pc board? ground layer. the data converter die attaches to an ep lead frame with the back of this frame exposed at the package bottom surface, facing the pc board side of the pack- age. this allows for a solid attachment of the package to the pc board with standard infrared (ir) reflow sol- dering techniques. a specially created land pattern on the pc board, matching the size of the ep (6mm x 6mm), ensures the proper attachment and grounding of the dac. place vias into the land area and implement 16-bit, 600msps, high-dynamic-performance dac with lvds inputs 12 ______________________________________________________________________________________ max5891 outp outn agnd 25 ? 50 ? 25 ? outp outn d0?15 lvds data inputs figure 6. differential output configuration max5891 outp av dd3.3 av dd1.8 dv dd3.3 dv dd1.8 av clk outn 0.1 f 3.3v voltage supply 0.1 f 0.1 f 0.1 f 1.8v voltage supply 0.1 f bypassing?ac level *ferrite beads d0?15 l vds data inputs * ** ** figure 7. recommended power-supply decoupling and bypassing circuitry
large ground planes in the pc board design to ensure the highest dynamic performance of the dac. connect the max5891 exposed paddle to the common connec- tion point of dgnd, agnd, and cgnd. vias connect the top land pattern to internal or external copper planes. use as many vias as possible to the ground plane to minimize inductance. the vias should have a diameter greater than 0.3mm. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. for a dac, the deviations are measured at every individual step. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step height and the ideal value of 1 lsb. offset error the offset error is the difference between the ideal and the actual offset current. for a dac, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the dac. this error affects all codes by the same amount. gain error a gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. settling time the settling time is the amount of time required from the start of a transition until the dac output settles its new output value to within the converter? specified accuracy. glitch impulse a glitch is generated when a dac switches between two codes. the largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. the glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. the glitch impluse is usually specified in pv s. dynamic performance parameter definitions signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog output (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical maxi- mum can be derived from the dac? resolution (n bits): snrdb = 6.02db x n + 1.76db however, noise sources such as thermal noise, refer- ence noise, clock jitter, etc., affect the ideal reading; therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spec- tral components minus the fundamental, the first four harmonics, and the dc offset. noise spectral density the dac output noise floor is the sum of the quantiza- tion noise and the output amplifier noise (thermal and shot noise). noise spectral density is the noise power in 1hz bandwidth, specified in dbfs/hz. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier frequency (maximum signal components) to the rms value of their next-largest distortion component. sfdr is usually measured in dbc and with respect to the carrier frequency amplitude or in dbfs with respect to the dac? full-scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. two-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc (or dbfs) of the worst 3rd-order imd differential product to either output tone. the two-tone imd performance of the max5891 is tested with the two individual output tone levels set to at least -6.5dbfs. adjacent channel leakage power ratio (aclr) commonly used in combination with wideband code- division multiple-access (wcdma), aclr reflects the leakage power ratio in db between the measured power within a channel relative to its adjacent channel. aclr provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited rf signal passes through a nonlinear device. max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs ______________________________________________________________________________________ 13
max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs 14 ______________________________________________________________________________________ pin configuration d4n 1 d3p 2 d3n 3 d2p 4 d2n 5 d1p 6 d1n 7 d0p 8 d0n 9 dgnd 10 dv dd3.3 11 pd 12 n.c. 13 av dd3.3 14 agnd 15 refio exposed paddle 16 fsadj 17 d12p 51 d13n 50 d13p 49 d14n 48 d14p 47 d15n 46 d15p 45 n.c. 44 n.c. 43 n.c. 42 av clk 41 cgnd 40 clkp 39 clkn 38 cgnd 37 av clk 36 av dd1.8 35 dacref 18 av dd1.8 19 agnd 20 av dd3.3 21 av dd3.3 22 agnd 23 agnd 24 av dd3.3 25 av dd3.3 26 agnd 27 outn 28 outp 29 agnd 30 av dd3.3 31 av dd3.3 32 agnd 33 av dd1.8 34 d4p 68 d5n 67 d5p 66 d6n 65 d6p 64 d7n 63 d7p 62 dv dd1.8 61 d8n 60 d8p 59 d9n 58 d9p 57 d10n 56 d10p 55 d11n 54 d11p 53 d12n 52 max5891 qfn-ep
max5891 16-bit, 600msps, high-dynamic-performance dac with lvds inputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm

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